Verilog for ASIC Design
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Sep 13, 2021 - Verilog
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sequence-detector
Here are 22 public repositories matching this topic...
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
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Dec 26, 2023 - Verilog
Verilog Mini Projects
verilog alarm-clock fifo vending-machine lfsr traffic-light-controller barrel-shifter voting-machine verilog-project carry-look-ahead-adder sequence-detector booth-multiplication
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Jun 13, 2025 - Verilog
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
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May 29, 2025
FSM: Sequence Detector using Verilog HDL
fsm verilog hdl verilog-hdl mealy-machine verilog-project verilog-code sequence-detector mealy-fsm sequence-detection sequence-detector-11010
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Jul 12, 2024 - Verilog
sequence detector with overlapped 2 patterns 010111 or 1101
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Aug 25, 2021 - Verilog
A hardware-based teaching aid for students to get familiarized with sequential logic using Basys FPGA boards.
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Nov 21, 2019 - HTML
Verilog Codes for various Design
pipeline multiplication verilog fifo uvm adder system-verilog verilog-hdl max-pooling sequence-detector one-detector reconfigurable-matrix-adder
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Nov 24, 2023 - SystemVerilog
All my submissions to assignments in CS254 - Digital Logic Design Lab ( Spring Course 2019 IIT BOMBAY)
stopwatch vhdl sdn-controller vendingmachine elevator-simulation traffic-signal-simulation sequence-detector
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Jul 15, 2020 - Rich Text Format
Generates a Finite State Machine to detect a binary sequence
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Jan 17, 2024 - C
Mealy Finite State Machine type overlapping sequence detector of "1011" in SystemVerilog.
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Mar 6, 2022 - SystemVerilog
Finite State Machines in Verilog — Moore FSM, Mealy FSM, Traffic Light Controller, Sequence Detector (1011), UART Transmitter, UART Receiver, SPI Master, Debounce Circuit | Step 4 of 8 toward a 16-bit pipelined RISC processor
fsm fpga verilog spi debounce uart icarus-verilog gtkwave vlsi digital-design traffic-light sequence-detector rtl-design mealy-fsm moore-fsm
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Jun 17, 2026 - Verilog
11001 sequence detector
asic fpga hardware verilog hdl digital-design hardware-description-language sequence-detector sequence-detection
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Jan 21, 2025 - Verilog
basic implementation of logic structures using verilog (revising github)
registers pipo d-flipflop full-adder sipo sequence-detector siso piso verilog-testbenches synchronous-counter priority-encoder jk-flipflop t-flipflop sr-flip-flop full-subtractor half-subtractor
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Feb 29, 2024 - Verilog
Digital Locker implemented in Verilog HDL using a Finite State Machine (FSM). Unlocks with sequence 1010, includes simulation, RTL schematic, and documentation.
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Sep 4, 2025 - Verilog
Detects the binary sequence 1010 using a high-speed Mealy FSM with TSPC D Flip-Flops in Cadence Virtuoso. Supports overlapping detection and transient verification (90 nm GPDK).
fsm simulation waveform schematic spectre vlsi state-diagram cadence-virtuoso cadence digital-design mealy-machine virtuoso d-flipflop sequence-detector tspc
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Jan 10, 2026
Binary pattern "1011" detector implemented using both Mealy and Moore FSM architectures. Comparative analysis of output timing, state usage, and architectural trade-offs with detailed waveform analysis and synthesis results.
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Aug 4, 2025 - Verilog
Phase-1 Cycle-1: RTL Coding Foundations
fsm traffic-light-controller sequential-logic arithmetic-logic-unit sequence-detector up-down-counter
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Dec 30, 2025 - Verilog
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