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stefand-0/README.md

Hello World!

I am stefpga, an amateur SystemVerilog developer who recently got their first FPGA! (Tang Nano 1K, upgrading to 9K soon). I have been studying SystemVerilog for around 5 months, and have already made some projects.

Projects:

• smallAES (Haven't implemented rounds properly)

• NeoH, a HDL which transpiles to SystemVerilog, proficient in creating easy and fast testbenches (not suited for RTL)

Pinned Loading

  1. neoh neoh Public

    NeoH (or NeoHDL) is a declarative HDL, proficient in creating extremely fast and secure testbenches, with complete support for SystemVerilog, as it transpiles into said HDL.

    Rust 2

  2. smallAES smallAES Public

    smallAES: A high-performance, iterative AES-128 cryptographic core written in SystemVerilog. Optimized for minimal LUT usage on resource-constrained FPGAs (like Tang Nano 1K). Includes a self-conta…

    SystemVerilog 1