Sexain-MemController

A simulator of a memory controller designed for hybrid DRAM+NVM.

Name		Name	Last commit message	Last commit date
Latest commit History 247 Commits
benchmarks		benchmarks
gem5-stable		gem5-stable
gem5run		gem5run
scripts		scripts
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
addr_trans_controller.cc		addr_trans_controller.cc
addr_trans_controller.h		addr_trans_controller.h
addr_trans_table.cc		addr_trans_table.cc
addr_trans_table.h		addr_trans_table.h
dram_banks.h		dram_banks.h
index_queue.cc		index_queue.cc
index_queue.h		index_queue.h
mem_store.h		mem_store.h
migration_controller.cc		migration_controller.cc
migration_controller.h		migration_controller.h
profiler.cc		profiler.cc
profiler.h		profiler.h
version_buffer.cc		version_buffer.cc
version_buffer.h		version_buffer.h

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