Pinned Loading

1. Clock_Domain_Crossing_Bridge Clock_Domain_Crossing_Bridge Public

   Simple CDC Bridge

   Verilog 2

2. FPGA_CW_6sem FPGA_CW_6sem Public

   FPGA coursework project on Verilog with GitHub workflow

   Verilog 8 1

3. Dual_Clock_FIFO Dual_Clock_FIFO Public

   Asynchronous FIFO

   Verilog 1

4. UART_Controller UART_Controller Public

   Parametrizable UART controller in Verilog with AXI-Stream interface, configurable baud rate, oversampling ratio, parity mode, stop bits, and regression testbench for verification.

   Verilog 1

5. Vivado_TCL_Tools Vivado_TCL_Tools Public

   Collection of Tcl scripts for Vivado FPGA workflow automation

   Tcl 1

6. YADRO-Multi-Clock YADRO-Multi-Clock Public

   Multi clock embedded system for MIK32

   C 1