I am an electrical/electronics engineer with a growing focus on digital IC design, RTL development, FPGA implementation, ASIC design flow, and VLSI systems. I enjoy taking hardware ideas from architecture and datapath thinking into Verilog modules, simulation, verification, and eventually synthesis-ready designs.
- BSc Electrical/Electronics Engineering
- MSc Biomedical Engineering, University of Toronto, with cross-disciplinary systems background
- Currently building projects in Verilog HDL, RTL design, and digital systems
- Interested in ASIC/FPGA design, computer architecture, verification, and hardware acceleration
- Reach me at famoustay55@gmail.com
- RTL Design: modular Verilog, parameterized datapaths, finite-state machines, counters, registers, ALUs, and digital control logic
- Verification: directed testbenches, waveform analysis, simulation transcripts, assertions, and self-checking testbench practices
- FPGA/ASIC Direction: synthesis-aware coding style, timing concepts, clock/reset discipline, and scalable hardware architecture
- Digital IC Foundations: CMOS logic, combinational/sequential circuits, datapath/control partitioning, and VLSI design methodology
| Stage | Area | Status |
|---|---|---|
| 1 | HDL Design — Verilog RTL (combinational, sequential, FSMs, parameterized) | ✅ Done |
| 2 | TCL Scripting — EDA flow automation | ✅ Done |
| 3 | Simulation & Verification — ModelSim / GTKWave, directed testbenches | ✅ Done |
| 4 | RTL-to-GDSII — OpenLane + SkyWater 130nm PDK (synthesis, P&R, DRC/LVS) | 🔧 Active |
| 5 | Timing Analysis — OpenSTA, setup/hold slack, SDC constraints | 🔜 Next |
| 6 | Formal Verification — SymbiYosys, SVA assertions | 🔜 Next |
| 7 | Low-Power Design — clock gating, UPF basics | 📅 Planned |
| 8 | Industry ASIC Flows — Synopsys DC, Cadence Innovus | 📅 Planned |
| 9 | Tape-out — Efabless / Google MPW open shuttle | 🎯 Goal |
- Parameterized Modular ALU in Verilog
Designed and verified a scalable ALU architecture with arithmetic, logic, comparison, and shift units using a decoder-controlled RTL hierarchy. - 8-Bit CPU Design in Verilog Designed and implemented a complete 8-bit CPU with ALU, registers, control unit, and instruction set using Verilog HDL.
- 8-Bit CPU RTL Synthesis Synthesized the 8-bit CPU RTL, mapped the design to SKY130 HD standard cells, and performed static timing analysis using a 100 MHz timing target.
- 16-Bit Register Design Designed and verified a parameterized 16-bit register file in Verilog for use in digital datapaths.
- Linear Feedback Shift Register (LFSR) Design Implemented a Verilog-based LFSR for pseudo-random sequence generation and digital testing applications.
